Segmented column memory array

Abstract

In an array of solid-state memory cells organized into rows and segmented columns and addressable by wordlines and bit lines, a memory cell within a segmented column is addressable by segment-select transistors which selectively connect the memory cell's pair of bit lines via conductive lines running parallel to the columns to a column decode circuit. The disposition of the segment-select transistors and the conductive lines relative to the segmented columns enables one segment-select transistor to fit in every two or more columns. In one embodiment, the segment-select transistors have double the pitch of the columns while the conductive lines have the same pitch of the columns. In another embodiment, the segment-select transistor have four times the pitch of the columns while the conductive lines have double the pitch of the columns. This enables the use of larger size segment-select transistors which are necessary for passing higher currents in devices such as EPROM or flash EEPROM. Column segmentation effectively isolates defects to individual segments and reduces the capacitance in the source and drain of an address memory cell.