Circuit for synchronous, glitch-free clock switching

Abstract

A circuit for synchronously selecting either a first or a second input clock signal as an output clock signal includes first and second logic means. The first logic means outputs a first clock signal when an internal control signal is at a first predetermined logic level, while the second logic means outputs a second input clock signal when the internal control signal is at a second predetermined logic level. A control logic means is utilized to select either the first or the second input clock signal as the output of the circuit by coupling the first input clock signal from the first logic means to the output when an input select signal is in a logic state. The second input clock signal is coupled to the output when the input select signal is in a second logic state. The control logic means generates the internal control signal in response to the input select signal. A transition of the input select signal from the first logic state to the second logic state causes the internal control signal to transition from the first predetermined logic level to the second predetermined logic level synchronous with the output clock signal. At the same time, the transition causes the control logic means to freeze the output before synchronously coupling the second input clock signal to the output such that the switching of the output clock signal from the first input clock to the second input clock signal occurs without glitching.