The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 1994

Filed:

Jan. 27, 1992
Applicant:
Inventor:

Takeshi Fukuda, Kanagawa, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257296 ; 257202 ; 257390 ; 257922 ;
Abstract

A semiconductor memory apparatus according to the present invention consists of memory cell forming regions, each formed in a rectangular plane form, a plurality of bit line pairs connected to a plurality of memory cells arranged and formed in these memory cell forming regions, and first and second peripheral circuits formed outside said memory cell forming regions, wherein said first and second peripheral circuits are formed and arranged symmetrically with respect to the point of intersection of two centerlines connecting the middle points of two opposite ones of the four sides of each of said memory cell forming regions, and said bit line pairs are connected to the first and second peripheral circuits. This configuration makes it possible to match the constituent elements of the peripheral circuits with each other and balance the bit line pairs, and thereby to prevent the drop in writing or reading rate and erroneous operations, to which semiconductor memory apparatuses according to the prior art are susceptible.


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