Very high density wafer scale device architecture

Abstract

This invention relates to the design and manufacture of a wafer-size integrated circuit. Lower layers of the wafer sized integrated circuit comprise electrically isolated repeating blocks such as logic elements or blocks of circuit elements. An upper conductive layer comprises data and address bus structures. A discretionary via layer located between the upper layer and the lower layers can be patterned. Patterning of the via layer avoids connecting the bus structure to defective elements or blocks, establishes addresses of elements, and establishes the organization of the addressing structure and data structure. The via layer is patterned to connect the upper bus lines to selected regions in the lower metal levels after testing for good and bad elements. The structure may include two or more address ports, which may simultaneously address different banks of the repeating elements, which feature is particularly useful for automatic refreshing of dynamic random access memories (DRAMs) and/or for plural addressing with other memory types. The architecture provides for flexibility in the final functional organization of wafer scale devices, which is determined at the time the via level is customized. An overall reduction of overhead control circuitry and the reduced size of the repeated block provides for higher total density per wafer than is achievable with conventional single chip integrated circuits using the same level of manufacturing technology.