Scsi controller and method for use on an information processing system

Abstract

An SCSI controller LSI comprising a CPU, command FIFO memories, a sequencer and a status register. The command FIFO memories store two commands issued consecutively by the CPU. The sequencer initially processes the first command, places a normal end code in the status register upon normal end of the command execution, and outputs a normal end interrupt set signal. At this point, a command indication bit for indicating the presence of an unexecuted bit is set. Then an AND gate inhibits the normal end interrupt set signal, and no interrupt signal is output. After the processing of the second command, the command indication bit is reset. This causes an interrupt signal to be output to the CPU. Thus when the first of the two consecutively issued commands ends normally, a normal end report to the CPU is omitted, and the interrupt signal for notifying the CPU of the normal end of command execution is inhibited.