The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 1994
Filed:
Jun. 15, 1992
Hiroshi Arimoto, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A quantum box semiconductor structure in which truncated triangular, or quadrilateral, pyramid base portions are formed on the main surface of a silicon semiconductor substrate defined, selectively, by a (111) B or a (100) plane; the triangular, or quadrilateral, truncated pyramid base portions have corresponding three, or four, (111) A plane sides, respectively. Corresponding triangular, or quadrilateral, quantum boxes of a second semiconductor material having a narrower energy band gap and larger electron affinity than the first, silicon semiconductor material of the base portions are formed on the corresponding triangular, or quadrilateral, top surfaces of the base portions and each has three, or four, corresponding (111) A plane sides. The quantum box lasers are formed in a succession of process steps including epitaxial growth or, alternatively, alternate epitaxial growth and etching steps. An alternative structure includes stripe-like quantum boxes of triangular cross-section. Further, the quantum boxes may be truncated and further triangular, or quadrilateral, prisms may be formed on the corresponding top surfaces of the respective boxes. A further embodiment employs truncated base portions of triangular prism cross-section and quantum wires of triangular cross-section formed thereon. Covering, clad and electrode interconnection layers are formed on the resulting structures and the main surface of the substrate, with respective electrodes being formed on the electrode interconnection layer and the bottom main surface of the substrate.