Driver for bus circuit of motor vehicle multiplex communications system

Abstract

A bus driver circuit for a multiplex communications system is configured from a limited number of components to withstand short circuiting of a connected bus circuit to voltage levels from ground potential to double conventional voltage levels encountered within a motor vehicle, i.e. twenty four (24) volts. The bus driver circuit does not interfere with bus operation if local power or ground is lost by one or more system node including the circuit, and can operate at relatively high frequencies, for example of approximately 83.3 to 166.7 kilobits per second (KBPS). Each line of a two-line bus is driven by a transistor whose current flow is limited by emitter degeneration and, in the case of the transistor which sinks current from the bus, a separate current control transistor which monitors current flow through its associated bus driver transistor and reduces its base drive at high temperatures to limit current flow therethrough and compensate the circuit for temperature variations. The turn-on and turn-off edges of bus driver signals are rounded by capacitors connected across the collector-base junctions of the bus driver transistors.