Selective bulk write operation

Abstract

A memory is disclosed having a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein. Each pair of bit lines is associated with one of the columns. A column decoder selects a column in the array responsive to a column address. A plurality of word line drivers selects, in response to a row address, a row of memory cells for connection with their associated pair of bit lines. A plurality of row isolation circuits isolates and enables a selected group of memory cells of each row from the remainder of the row in response to a bulk write signal. Each row isolation circuit has a conduction path between its associated word line driver and the selected memory cells in the associated row. A bulk write signal is sent to each column containing the selected memory cells. A first logic state is then written into the selected memory cells in response to the bulk write signal.