Tristate data output buffer having reduced switching noise and

Abstract

A data output buffer suitable for use in a semiconductor memory device includes a first input circuit coupled to a first data signal and a first control signal, e.g., an output enable signal, and a second input circuit coupled to a second data signal which is the inverse of the first data signal and the first control signal. The data output buffer also includes a pull-up circuit responsive to the output of the first input circuit for selectively raising the data output node to a high voltage level, e.g., Vcc, and a pull-down circuit responsive to the output of the second input circuit for selectively lowering the data output node to a low voltage level, e.g., Vss. The data output buffer further includes a preset circuit comprised of a first preset control circuit responsive to the output of the first input circuit and a second control signal, e.g., an inverse output enable signal, for selectively raising the data output node from the low voltage level to an intermediate voltage level, e.g., 1/2 Vcc, and a second preset control circuit responsive to the output of the second input circuit and the second control signal for selectively lowering the data output node from the high voltage level to the intermediate voltage level. The preset control circuit advantageously operates to maintain the data output node at the intermediate voltage level during active states of the output enable signal without generating any DC current, thereby eliminating the noise and reliability problems of presently available data output buffers.