The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 1994
Filed:
Jul. 28, 1992
Michael D Rostoker, San Jose, CA (US);
Mark Schneider, San Jose, CA (US);
Edwin Fulcher, Palo Alto, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A first, lower heat sink disposed immediately below and closely adjacent a semiconductor chip (die) in a semiconductor chip assembly is disclosed. The lower heat sink is a flat metallic or ceramic shim. A second, upper heat sink disposed immediately above and closely adjacent the top surface of the semiconductor device is disclosed. The upper heat sink may have a portion in contact with a passivation layer over the top surface of the semiconductor die (device). The second heat sink preferably has a flat surface forming an exterior surface of the semiconductor device assembly. In one embodiment, the second heat sink has pedestals resting atop a plastic layer in a tape-like structure within the semiconductor chip assembly. In a second embodiment, the second heat sink includes an add-on portion that is external to the semiconductor chip assembly. The first heat sink is particularly well-suited to applications wherein the semiconductor chip assembly is mounted to a thermal mass. The second heat sink is particularly well-suited to applications wherein air cooling is available. Each of the first and second heat sinks provide effective cooling, and when used together provide even more effective cooling. Alternatively, the die may be mounted to the top surface of a printed circuit board support structure, the bottom surface of which is provided with a plurality of solder bumps.