The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 1994
Filed:
Jul. 16, 1990
Tomohiro Marui, Chiba, JP;
Hideyo Funatsu, Chiba, JP;
Kawasaki Steel Corp., Hyogo, JP;
Abstract
A system and method for automatically and optimally determining a route to be wired in a Programmable Logic Device (PLD) are disclosed in which a plurality of load pins to be wired with a source pin are selected sequentially according to a shortest length of distance from the source pin to the respective load pins, a plurality of switching stations present midway through each route of paths are selected on the basis of coordinates of a center of gravity derived from the coordinates of the unwired load pins and distances to the respective load pins to be wired sequentially, and, thus, a line network constituted by the routes of the first and second paths is formed. Furthermore, the route is corrected by searching out any of problematic switching stations through which the path cannot be formed from among the switching stations present along the route so as to bypass the problematic switching station. If this correction proves impossible, a second correction is sought by searching the problematic switching station itself so as to bypass a wired path present within the problematic switching station. If this correction also fails, a third mode of correction is implemented in which a switching station adjacent the problematic switching station is utilized.