Variable-length code decoding device

Abstract

A variable-length code decoding device includes a serial-to-parallel converter for converting serial data into parallel data for every N bits where N is an integer. The serial data includes consecutive data pieces having variable data lengths. A buffer stores the parallel data which is sequentially read out therefrom for every 2 N bits and which is shifted by N bits in a high-order-bit direction in response to a carry signal. A register stores a shifted number 'j' which is read out therefrom in response to a clock signal. The shifted number 'j' indicates the number of bits to be shifted. A barrel shifter receives the parallel data from the buffer memory and shifts, by the shifted number 'j', the parallel data in the high-order-bit direction so that N-bit parallel data having a starting bit which corresponds to an (j+1)th bit of the parallel data from a most significant bit thereof is output from the barrel shifter. A shifted number/carry signal generator generates, on the basis of a code length of effective data contained in the N-bit parallel data and the shifted number stored in the register, an updated shifted number and the carry signal. The shifted number stored in the register is updated by the updated shifted number.