The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 1994

Filed:

May. 08, 1992
Applicant:
Inventors:

Yukihiro Saeki, Tokyo, JP;

Hiroki Muroga, Tokyo, JP;

Tomohisa Shigematsu, Tokyo, JP;

Toshio Hibi, Tokyo, JP;

Yasuo Kawahara, Tokyo, JP;

Kazunao Maru, Tokyo, JP;

Kenneth Austin, Northwich, GB;

Gordon S Work, Warrington, GB;

Darren M Wedgwood, Warrington, GB;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307465 ; 307480 ; 307243 ;
Abstract

A programmable logic unit circuit comprising a data memory circuit, a combinational logic circuit supplied with at least two input signals, two input select circuits for, based on the stored data in the data memory circuit, selecting the two input signals supplied to the combinational logic circuit from more than two input signals, a clock-synchronized circuit for supplying the output signal from the combinational logic circuit in synchronization with a clock signal, and a 3-state-output type output select circuit for selecting either the output signal of the combinational logic circuit or the output signal of the clock-synchronized circuit, depending on the stored data in the data memory circuit.


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