The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 1994
Filed:
Jul. 08, 1992
Lawrence D Curley, Endwell, NY (US);
Matthew J Mitchell, Jr, Endicott, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A power-on reset circuit is used to initialize a system component upon power-on. The circuit comprises a digital circuit such as a shift register which exhibits a multiplicity of uncertain or random outputs upon power-on. These output are coupled to digital logic such as an AND gate which itself outputs a power-on reset signal when any of the outputs of the shift register is not a predetermined output level. Because the outputs of the shift register are uncertain or arbitrary upon power-on and there are a multiplicity of such outputs, it is not likely that all of the outputs of the shift register will coincidentally exhibit the predetermined levels upon power-on. Consequently, it is very likely that the AND gate will provide the power-on reset signal upon power-on to initialize the system component. Subsequently, when the system is ready for normal operation, the shift register is set with the predetermined levels to terminate the power-on reset signal and thereby enable or condition the system component for normal operation.