The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 1994
Filed:
Jun. 22, 1992
Joel D Lamb, Ft. Collins, CO (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
A clocking methodology for VLSI chips which uses global overlapping clocks, locally or remotely generated non-overlapping clocks, combined with pipeline control signals to generate signals which control the transfer gates of registers in a pipeline. The signals which control the transfer gates of the registers in a pipeline maintain the important timing relationships of the non-overlapping clock signals combined with the control signals. The global overlapping clocks are used where possible to provide timing advantages, while the non-overlapping clocks are used to eliminate race conditions as data propagates down a pipeline of transparent registers. Overlapping clock signals are used whenever such race conditions can be avoided, as at the ends of the registered pipeline, with the resultant performance improvement.