Semiconductor memory device and production process thereof

Abstract

A semiconductor memory device is highly integrated by a combination of planer cell structure with the trench etching technique. Trenches are formed on a substrate in parallel with each other, and diffused layers are on sidewalls of the trenches to provide bit lines. Gates oxide layers are formed on the bottoms of trenches and on surfaces of the substrate between adjacent two trenches, and silicon oxide layers thicker than the gate oxide layers are on the bit lines. Word lines are formed in band in parallel with each other in a direction to cross the trenches perpendicularly thereto. Channel regions are defined in portions of word lines on the bottoms of trenches and on the surfaces of substrate crossed thereby. Ion implantation is conducted into each memory transistor according to data to determine a ROM code, to set a threshold value therein.