The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 1994
Filed:
Dec. 22, 1992
Christopher M Schreiber, Newport Beach, CA (US);
Haim Feigenbaum, Irvine, CA (US);
Harold C Bowers, Rancho Palos Verdes, CA (US);
Hughes Aircraft Company, Los Angeles, CA (US);
Abstract
A multi-level substrate (24) for mounting and interconnecting a number of integrated circuit chips (10) is formed of a stack of laminated sheets each comprising a conductive circuit layer (30,34,38,42,46) is laminated to a dielectric film (32,36,40,44,48). The sheets are formed by fully additive or semi-additive processes on a reusable mandrel and are interconnected to one another by raised features (78) on the circuit layer of one sheet that project through a hole (86) in the dielectric film of an adjacent sheet to contact a receiving area (88) of the circuit layer of the adjacent sheet. Integrated circuit chips (10) and other electrical components are mounted to the uppermost sheet and electrically connected thereto by means of wiring bonding (16) or a f lip-chip arrangement (150) in which chip pads (148) rest upon and contact raised features (146) of the circuit layer (140) of the uppermost sheet.