The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 1994
Filed:
Jul. 26, 1990
Xiwen Ma, Santa Clara, CA (US);
Hongmin Zhang, Santa Clara, CA (US);
Weidong Xu, Santa Clara, CA (US);
Apt Instruments (N.A.) Inc., Santa Clara, CA (US);
Abstract
A fuzzy inference system and its method of operation. The system comprises an inference unit (30) of pipeline architecture, a control unit (20) for controlling the operation of the inference unit, and a host computer (10) for supervising the entire operation. A plurality of inference rule groups (referred to as rule cells) each for controlling an object to be controlled are stored in a rule memory (22) of the control unit (20). The rule cell is composed of a number of path codes. The path code includes object data to be processed and operation codes. The operation codes are to control each of processing/operation sections (31 to 35) of the inference unit (30). After the host computer has set a rule cell address for designating a rule cell in the rule memory (22) to a rule cell address register (23) in order to execute an inference, when a path address counter (24) is started, path addresses are outputted from the counter (24) in sequence, so that path codes within the designated rule cell are read and supplied to the inference unit in sequence. The inference unit executes a fuzzy inference by a pipeline processing method on the basis of the supplied path codes. Timing signals are fed to each of the processing/operation sections (31 to 35) from a controller (21). When an inference end signal is applied to the host computer via the controller, the host computer reads the inference results from an output buffer (35), designates a succeeding rule cell for executing a succeeding inference, and starts the path address counter (24) again.