Semiconductor memory device and method of testing the same

Abstract

A sense.multidot.input/output gate includes MOS transistors which are provided for each bit line pair and have their gates and drains cross-coupled together, separating transistors arranged between the gates and the drains of the MOS transistors, and column selecting gates connecting the drains of the MOS transistors to internal data transmitting lines. The semiconductor memory device further includes a load circuit which precharges the internal data transmitting lines to a predetermined potential in a test mode, and a line test circuit which determines existence and nonexistence of a defective memory cell based on the potentials of the internal data transmitting lines. In the data reading operation, the column selecting gates become conductive while the separating transistors are in OFF state, and the potential of the internal data transmitting line changes by virtue of the discharge through one of the cross-coupled MOS transistors. In this construction, the sense amplifier is used also as the read gate. Therefore, high-speed reading of data is allowed, and tests for many memory cells in up to one row can be simultaneously performed. Accordingly, a test time is reduced in a highly integrated semiconductor memory device.