The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 1994

Filed:

Jul. 12, 1993
Applicant:
Inventors:

Shinji Saito, Kasugai, JP;

Akira Kobayashi, Kasugai, JP;

Assignee:

Fujitsu Limited, Kasugai, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L / ; H03L / ; H03L / ;
U.S. Cl.
CPC ...
331 / ; 331 14 ; 331 16 ; 331 25 ; 331D / ;
Abstract

This invention aims at providing a PLL synthesizer circuit that can shorten lock-up time while sufficiently securing a time constant of a low-pass filter, and has a structure wherein a phase comparator 3 outputs output signals .phi.R and .phi.P on the basis of a reference signal fr output from a reference frequency divider 2, and a comparison signal fp output from a comparison frequency divider 4; the output signals .phi.R and .phi.P are negatively fed back to the comparison frequency divider 4 through a charge pump 5, a low-pass filter 6 and a voltage controlled oscillator 7, and a lock detection circuit 8 outputs a lock signal LD when in a locked state. When an output signal SVCO of the voltage control oscillator 7 coincides with a set frequency, when the lock detection circuit 8 does not output the lock signal LD, a reset circuit 15 outputs a reset signal PC to the reference frequency divider 2 and to the comparison frequency divider 4, and the reset signal PC brings the phase of the reference signal fr into conformity with the phase of the comparison signal fp.


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