The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 1994

Filed:

Mar. 05, 1992
Applicant:
Inventor:

Hironori Nagasawa, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307448 ; 307450 ;
Abstract

A buffer logic circuit having a lightly doped drain structure, comprising a power source potential, a ground potential, first and second Field Effect Transistors having drain electrodes, gate electrodes supplied with first input signal and a second input signal, respectively, source electrodes being connected to each other, and the drain electrodes for generating output signals corresponding to the input signals, respectively, device, having an end connected to the source electrodes of the first and second FETs, for reducing the potential of the drain electrodes, and device, connected between the other end of the drain electrode potential reducing device and the ground potential, for supplying a constant-current regulated power.


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