Comparator circuit comprising input signal attenuator

Abstract

A comparator circuit comprising a comparator which includes a first and a second supply terminal for connection to a supply voltage. A first input terminal is connected to a reference voltage and a second input terminal is connected via an attenuation circuit to a signal terminal for connection to an input voltage. The attenuation circuit includes a resistor, a bias voltage terminal for connection to a bias voltage, and a MOS transistor having a gate (g), backgate (bg), source (s) and drain (d). The drain is connected to the signal terminal and the source and the backgate are connected to the second input terminal. The gate is connected to the bias voltage terminal and the resistor is inserted between the gate and the source of the transistor. In the case of high input voltages on the signal terminal, the MOS transistor operates in its saturation range and the voltage on the source continues to be substantially equal to the bias voltage. If the drain voltage falls below the bias voltage (Vbias), the MOS transistor is rendered conductive in the linear range and the voltage on the source follows the voltage on the drain. The comparator thus is protected against excess voltage on the second input terminal.