High voltage field effect transistor having a small ratio of channel

Abstract

The present invention is directed to a high voltage field effect transistor (FET) constructed on the major surface of a substrate of a first conductivity type. The FET includes a drain region of a second conductivity type located in the major surface and a generally annular drift region of the second conductivity type, located in the major surface and outside of the drain region. A generally annular gate is located on the major surface and outside of the drift region, and a generally annular source region is located in the major surface and outside of the gate. A first channel stop is located in the major surface and outboard of the source region, and a second channel stop located in the major surface and beneath the gate, having at least two portions in close proximity to each other. A channel region is located in the major surface and between the two second channel stop portions. The second channel stop blocks communication between the source region and the drift region except through the channel region.