The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 1994
Filed:
Jun. 24, 1991
David C Oliver, Maple Hts., OH (US);
Micheal J Petrillo, Euclid, OH (US);
John F Vesel, Willowick, OH (US);
Picker International, Inc., Highland Hts., OH (US);
Abstract
Pixel values f(m,n) of an image are reduced (A) by predicting each pixel value based on preceding pixel values and retaining the deviation e(m,n) between the actual and predicted values. The reduced values e(m,n) are serially fed to an input latch (20). A latched sizer (22) determines the larger of the number of bits of the value in the input latch and the largest previously received reduced value e(m,n). A comparator (42) compares a number of bits from the latched sizer with the number of bits per field indicated by a look-up table (44). Each time another reduced value e(m,n) is received, a state counter (46) indexes one state, i.e., increases the number of bit fields per output word and, when necessary causes the look-up table (44) to reduce the number of bits per field. When the comparator (42) determines that the number of bits from the latched sizer will not fit in the bit field size indicated by look-up table (44), a bit shuffler (C) is caused to form a packed word from the precedingly received reduced values. When the number of bits does fit into the bit field, the reduced value in the input latch (20) is forwarded to the bit shuffler and the process repeated with the next reduced value.