The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 1994
Filed:
Dec. 19, 1990
Katsuyuki Suzuki, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A predetermined number of logical page addresses are effectively translated into corresponding real ones. The number of the logical page addresses is determined by (M+N) bits and, each of the logical page addresses includes upper M-bit and lower N-bit. Logical page address registers, whose number is equal to 2.sup.N, are provided to respectively store the predetermined number of logical page addresses applied. Address translation buffers (whose number is also equal to 2.sup.N) each stores 2.sup.M real page addresses which are grouped according to each of the lower N bits. The address translation buffers receive the upper M-bit of one of the logical page addresses, and output real addresses. An address translation controller receives the outputs of the address translation buffers and also receives the lower N-bit, and selects the real page addresses using the lower N-bit. The selected real page addresses are applied to a plurality of real address registers. A page number comparator determines whether or not the upper M-bit of one of the logical page address coincides with the upper M-bit of each of the remaining logical page addresses. The page number comparator outputs the comparison results which allow the real address(es) stored in the real address registers to be applied to a main memory.