High precision phase comparator and phase locked loop

Abstract

A modulus counter counts first clock pulses to modulus M and outputs the count value as an m-bit reference signal, M being an integer. A latch circuit samples and holds the reference signal in response to a trigger signal generated by a trigger signal generator in synchronism with an input signal. A high-speed counter is supplied with second clock pulses of a frequency higher than that of the first clock pulses and starts counting the second clock pulses in response to the trigger signal and stops the counting in response to a first one of the first clock pulses immediately thereafter. A data processor converts the n-bit count value of the high-speed counter to n-bit data corresponding to a phase fraction of a phase quantization step in the latch, combines the n-bit data as low-order bits with m-bit data from the latch and outputs the combined data as phase difference data.