The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 1994
Filed:
May. 19, 1992
Masashige Tada, Itami, JP;
Takehiko Umeyama, Itami, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
An integrated circuit (IC 101) has ECL circuits (E3 to En). Bias current (I3) applied to the ECL circuit (E3) is fed by a current mirror circuit consisting of transistors (Q3 and Q1) and resistors (R2 and R3). Constant current (IO) flows in the transistor (Q1) by a constant current circuit (4). The transistor (Q1) has its collector connected to one end of a resistor (R1), the other end of which is connected to a test terminal (2). With an outside resistor (Rb) connected to the test terminal (2) of the integrated circuit (IC 101), part of the constant current (IO) is pulled out to the outside, and the current flowing in the resistor (R2) becomes small. Accordingly, the bias current (I3) is reduced. A voltage difference .DELTA.V of logic states in the ECL circuit (E3) can be controlled from the outside without controlling a temperature, and a test of an inferior transistor the ECL circuit (E3) has can be performed.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile