Circuit for slowing portion of microprocessor operating cycle in all

Abstract

Conventional microprocessors await the data on the bus for acceptance for a given number of processor clock signals after accessing an external device, notably after a read instruction for an external data memory. When a comparatively slow memory is used in conjunction with a fast microprocessor, it may occur that the data is not yet present at the anticipated instant. In microprocessors in which no hold state is provided it is known to reduce the clock frequency during the reading of the external memory until the data is actually available. However, this results in a fluctuating mean clock frequency of the microprocessor so that internal timing members, controlled by the clock, cannot determine defined periods of time. In accordance with the invention, the clock frequency is reduced during the part of the operating cycle of the microprocessor during which an external device can be accessed, the microprocessor operating at the maximum clock frequency during the remainder of the cycle. This also occurs when actually no access takes place, but the mean clock frequency of the microprocessor is then constant so that internal timing members can still utilize the clock signal. Steps are proposed to adapt the part of the operating cycle of the microprocessor during which the clock frequency is reduced as accurately as possible to the part of the cycle between the initiation of the access or the reading and the actual delivery of the data.