The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 05, 1994
Filed:
May. 21, 1993
Michio Shimada, Tokyo, JP;
NEC Corporation, , JP;
Abstract
A hardware arrangement is provided for transforming plaintext into corresponding ciphertext. The plaintext includes a plurality of words each having a predetermined bit length. The hardware arrangement sequentially acquires the words and exhibits a predetermined number of arithmetic operations on the word acquired. Each of the arithmetic operations includes a plurality of arithmetic processes. The hardware arrangement outputs an enciphered word therefrom when completing the predetermined number of arithmetic operations. A selector is arranged to receive two inputs and selectively output one of the two inputs. One of the two inputs corresponds to the word acquired. A multiplier is coupled to receive the output of the selector. The multiplier multiplies the output of the selector by a multiplier and outputs a product therefrom. An adder is coupled to receive the product. The adder adds the product and an addend and then outputs a sum. A divider is coupled to receive the sum such as to divide the sum by a modulus and outputs a residue therefrom. The value of the modulus is subject to change at each of the arithmetic operations. The residue is applied to the selector as the other of the two inputs.