The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 05, 1994
Filed:
Dec. 15, 1992
Takeshi Ikenaga, Kanagawa, JP;
Jun-ichi Takahashi, Kanagawa, JP;
Abstract
A built-in self test circuit includes a pattern generator, a functional block subjected to a self test on the basis of an output from the pattern generator, a space compressor for compressing a test result of the functional block, and a comparator for comparing an output from the space compressor with an expected value and outputting a comparison result. The functional block has O (positive integer) inputs and M (positive integer) outputs. The pattern generator is constituted by a linear feedback shift register, having an output bit width P (P=O/N) which is 1/N of the inputs O of the functional block, for generating a pseudorandom pattern and an iterative pseudorandom pattern output unit for distributing outputs from the linear feedback shift register in units of N outputs and outputting, to the functional block, an iterative pseudorandom pattern output having an iterative O-bit width (O=P*N) of the pseudorandom pattern output from the linear feedback shift register every P bits. The space compressor has a function of spatially compressing the M outputs from the functional block into L outputs (positive integer and M>L). The pattern generator, the functional block, the space compressor, and the comparator are built into a semiconductor chip into which other functional elements are built.