The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 1994

Filed:

Sep. 10, 1991
Applicant:
Inventor:

Kaoru Hama, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365154 ; 365156 ; 365190 ;
Abstract

A memory cell of a static semiconductor memory device includes first and second inverters, first and second variable resistors and first and second transfer transistors. The first variable resistor is connected between an output terminal of the first inverter and an input terminal of the second inverter. The second variable resistor is connected between an output terminal of the second inverter and an input terminal of the first inverter. The first transfer transistor has a current path connected between the output terminal of the first inverter and a first bit line and a gate connected to a word line. The second transfer transistor has a current path connected between the output terminal of the second inverter and a second bit line and a gate connected to the word line. A control circuit controls the resistances of the first and second variable resistors, and the resistances of the first and second variable resistors are controlled to be reduced when a memory cell is selected in the write-in cycle and they are increased when the memory cell is not selected.


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