The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 1994

Filed:

Nov. 17, 1992
Applicant:
Inventors:

Kouichi Yamazaki, Maebashi, JP;

Setsuo Ogura, Takasaki, JP;

Kazuyuki Kamegaki, Sawa, JP;

Kenya Yamauchi, Takasaki, JP;

Yukinori Kitamura, Takasaki, JP;

Tuyoshi Nagase, Maebashi, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257207 ; 257210 ; 257211 ; 257758 ; 257776 ;
Abstract

When a semiconductor integrated circuit device having a wiring structure of three or more layers is hierarchically considered as a collection of a plurality of functional blocks, each functional block is internally connected by wirings in the first wiring layer, in which wirings have their main extended direction prescribed to be the X-direction, and wirings in the second wiring layer, in which wirings have their main extended direction prescribed to be the Y-direction, formed over the first wiring layer. Wirings in the third wiring layer, in which wirings have their main extended direction prescribed to be the same as the wirings in the second wiring layer, formed over the second wiring layer, together with wirings in the first and second wiring layer, are used as signal wirings between functional blocks, while the wirings in the third wiring layer are used as power supply wirings for providing power supply to functional blocks. As the power supply paths to functional blocks, a plurality of power supply wirings are branched off from the power supply electrode such as a power supply pad and terminated there. The power supply electrode on the high voltage side and the power supply electrode on the low voltage side are disposed separately at opposing edge portions of the semiconductor substrate and the power supply wirings proceeding therefrom to their target functional blocks are bent in the vicinity of the edge portion of the semiconductor substrate and therefrom extended straight to the target points.


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