The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 1994

Filed:

Jun. 05, 1991
Applicant:
Inventors:

Jacquelin Babakanian, Boca Raton, FL (US);

James W Davis, Delray Beach, FL (US);

Mark S Garvin, Boca Raton, FL (US);

Robert M Swanson, Boca Raton, FL (US);

Nandor G Thoma, Boca Raton, FL (US);

David M Wu, Boca Raton, FL (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364488 ; 371 223 ; 371 225 ;
Abstract

Groups of DCVS (Differential Cascode Voltage Switch) circuits are interconnected by single-track data transfer connections. Each group contains one or more DCVS tree circuits, through which data signals propagate only on dual-track connections. In each group, at least one DCVS tree circuit is configured as an input boundary tree, and at least one tree circuit is configured as an output boundary tree. All data inputs externally applied to a group, are transferred only through input boundary trees of the group, and all data outputs transferred out of a group leave the group only through output boundary trees of the group. If a group has only a single tree, that tree serves as input and output boundary tree of the group. Each input boundary tree of each group has one or more associated primary shift register latch (SRL) circuits through which all external data inputs to that tree are transferred. Such external data inputs are received through the single-track connections mentioned above. The primary SRL circuits are also used to present predeterminable test data inputs to respective trees, and to collect primary test data outputs representing signals received through the single-track connections. In such usage, the SRL circuits are connected as a scannable shift register. Each output boundary tree has an exclusive-OR (XOR) circuit for indicating if the respective tree is in a legal or illegal state. The XOR circuits connect to secondary scannable SRL circuits for external presentation of illegal state indication. The primary test data outputs together with the externally presented illegal state indications form a basis for detecting and locating any faulty state in any group.


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