Line data-block data converting circuit

Abstract

A converting circuit has a memory of a capacity of at least n.times.b.sub.max pixels when b.sub.max is set to the number of valid pixels in a frequency mode providing a largest number of valid pixels for one horizontal period with respect to a plurality of frequency modes. A memory controller has a read only memory (ROM) table for storing an address generating order in advance in the frequency mode of the number b.sub.max of valid pixels. In the memory controller, an address is generated in accordance with address generating order stored in the ROM table when line data in another frequency mode are stored in the memory. Data of n.times.b valid pixels are stored in the memory every n horizontal periods when the number of valid pixels for one horizontal period in the other frequency mode is set to b. In the memory controller, data of invalid pixels are store in the memory at the remaining n.times.b.sub.max -n.times.b addresses. A data mask inhibits data of (b.sub.max /n)-(b/n) invalid pixel blocks every n horizontal periods with respect to block data read and converted at a reading time from being outputted to the next stage.