The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 1994
Filed:
Apr. 08, 1993
Tim Garverick, Cupertino, CA (US);
Jim Sutherland, Sunnyvale, CA (US);
Sanjay Popli, Sunnyvale, CA (US);
Venkata Alturi, Sunnyvale, CA (US);
Arthur Smith, Jr, San Carlos, CA (US);
Scott Pickett, Los Gatos, CA (US);
David Hawley, Belmont, CA (US);
Shao-Pin Chen, San Jose, CA (US);
Shankar Moni, Santa Clara, CA (US);
Benjamin S Ting, Saratoga, CA (US);
Rafael C Camarota, San Jose, CA (US);
Shin-Mann Day, Sunnyvale, CA (US);
Frederick Furtek, Menlo Park, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A low transistor count programmable bussing resource for a programmable logic array allows the use of the bussing resources as inputs or outputs to a cell in the array and allows connections between different buses without effecting the normal use of the cell. The bussing resource allows efficient routing of signals between cells and is symmetric to allow rotation of logic macros built using combinations of cells and buses.