Digital clock dejitter circuits for regenerating clock signals with

Abstract

A digital clock dejitter circuit has a RAM for receiving an incoming gapped signal, a digital, fractional RAM fullness gauge for tracking the average input and output rates to and from the RAM and for generating therefrom a control indication, and a controllable digital frequency generator for receiving a fast clock signal and the control indication, and for providing therefrom a substantially jitter-free clock signal at the same nominal rate as the incoming gapped signal. The RAM fullness gauge has write and read counters which track the movement of data into and out of the RAM, and a subtractor for taking the difference of the counters to obtain the integer value of the RAM depth. The controllable digital frequency generator has an adder, a register, and a fast clock counter (FCC) which provides the fullness gauge with a fractional digital indication of the RAM depth. The adder has a carry output fed to the FCC to control whether the FCC divides by x or x+1, and a remainder output fed to the register and then fed back as an input to the adder. The adder also receives the control indication from the fullness gauge as an input. FCC inputs include the fast clock, and the carry output of the adder. The FCC outputs are a read signal for causing a byte to be read from the RAM at the end of a count cycle, and the fast clock count used for fractional fullness.