The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 1994
Filed:
Jun. 18, 1993
Applicant:
Inventors:
Jim Sutherland, Sunnyvale, CA (US);
Sanjay Popli, Sunnyvale, CA (US);
Venkata Alturi, Sunnyvale, CA (US);
Frederick Furtek, Menlo Park, CA (US);
Assignee:
National Semiconductor Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
3074651 ; 307465 ; 3073031 ;
Abstract
The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a matrix that includes a plurality of horizontal rows of logic cells and a plurality of vertical columns of logic cells. Adjacent abutting cells logic cells are interconnectable via horizontal and vertical configurable interconnections running between adjacent cells. Furthermore, configurable diagonal interconnections run between diagonally adjacent abutting logic cells in the array.