The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 1994

Filed:

Mar. 06, 1991
Applicant:
Inventors:

Sheldon Aronowitz, San Jose, CA (US);

Courtney Hart, Los Gatos, CA (US);

Court Skinner, East Palo Alto, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 24 ; 437 34 ; 437 45 ; 437131 ; 257281 ; 257409 ; 257410 ; 148D / ; 148D / ;
Abstract

Germanium is used to significantly enhance the drift mobilities of minority carriers in the channels of N-channel and P-channel metal-oxide-semiconductor (MOS) transistors with silicon substrates. Germanium processing is also used to enhance the source/drain contact conductance for MOS devices. Methods are disclosed for forming the germanium-rich interfacial layer utilizing a germanium implant and wet oxidation or growing a silicon-germanium alloy by molecular beam epitaxy.


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Aronowitz, Sheldon. (1994). Method of providing lower contact resistance in mos transistor structures (U.S. Patent No. 5296386). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5296386

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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