The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 1994
Filed:
May. 31, 1991
Richard D Pribnow, Chippewa Falls, WI (US);
Cray Research Systems, Inc., Minneapolis, MN (US);
Abstract
The present invention provides an apparatus for monitoring access by a processor in a computing system to certain defined portions of memory. According to the present invention, the user specifies an address or range of address (the 'watchword') in memory to be monitored. Each processor contains hardware which monitors outgoing memory references. If the processor attempts to access the defined portion of memory, the present invention generates a signal which is sent back to the issuing processor to inform it that referenced the watchword in memory. The present invention has several applications. In particular however, the present invention can be used in conjunction with debugging software packages as an aid for debugging user software programs on multiprocessing computer systems. Specifically, the present invention can be used to pinpoint which processor in a multiprocessing computer system accessed the watchword portion of memory. For example, if a processor executed an instruction containing an error, causing improper calculation of a write destination address which resulted in data errors in memory, the present invention can pinpoint precisely which processor in the multiprocessing computer system executed the erroneous instruction, thus pinpointing the erroneous code to within a few instructions. An additional feature of the present invention is that it operates wholly independently and in parallel with the output circuitry of a processor. Thus, no additional levels of logic are introduced into the processor-to-memory path, and as a result the present invention does not adversely impact overall system performance.