Addressing system free from multi-selection of word lines

Abstract

An addressing system comprises an address buffer unit responsive to a clock signal of a low level for latching an address signal indicative of one of word lines, and maintaining the address signal until the clock signal is shifted to from a high level to the low level again; an address decoder unit coupled with the address buffer unit for selectively driving decoded signal lines; a timing control unit responsive to the clock signal for producing an in-phase timing signal; and a driver unit having a plurality of driver circuits respectively coupled between the decoded signal lines and the plurality of word lines, wherein the plurality of driver circuits are operative to respectively latch logic levels on the associated decoded signal lines when the in-phase timing signal is shifted from the low level to the high level so as to selectively drive the address lines to active level, and maintains all of the word lines in inactive level while the in-phase timing signal remains in the low level, thereby preventing the word lines from multiple selection.