The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 1994
Filed:
Nov. 25, 1992
Richard T Simko, Los Altos, CA (US);
Information Storage Devices, San Jose, CA (US);
Abstract
The present invention discloses methods and apparatus for implementing a single-transistor cell EEPROM array for analog or digital storage. The single-transistor storage cell is made possible by continuously maintaining a net negative charge on the floating gate of the EEPROM storage transistor. Furthermore, according to the present invention, a dense layout of the single-transistor cells is possible by sharing a common diffusion region between the transistors located in the same row and the transistors located in one adjacent row. This common diffusion region functions as a source in the erase and program modes, and as a drain in the read mode. Moreover, the common diffusion feature of the present invention allows the use of a single level of metal in distributing the various operating voltages to the EEPROM storage transistors. Further, utilizing a single level of metal allows for a simple and dense fabrication and also reduces the parasitic capacitances in the EEPROM storage array. Array operating voltages are chosen such that 'program disturbance' is eliminated on cells adjacent to a cell undergoing programming. Finally, the present invention utilizes only a single polarity of operating voltages.