Memory access control device having bank access checking circuits

Abstract

In a memory access control device (10) for use in controlling access by at least one address signal to a memory device (11) comprising memory modules each of which comprises a plurality of memory banks, a module checking circuit (16) checks first and second module signals indicative of the memory modules to produce a module coincidence signal when the first and the second module signals coincide with each other. First and second bank access checking circuits (17, 18) are assigned with first and second preselected number of memory modules and check first and second bank address signals indicative of the memory banks and first and second bank access held signals indicative of at least two of the memory banks which should be accessed. The first and the second bank access checking circuits produce first and second bank coincidence signals when the first and the second bank address signals coincide with the first and the second bank access held signals. An access judging circuit (191) alternatingly produces first and second inhibit signals in response to the module coincidence signal. The first and the second inhibit signals are also produced in response to the first and the second bank coincidence signals. An access signal output control circuit (20) inhibits supply of the address signal as first and second address signals to the memory device in response to the first and the second inhibit signals.