The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 1994

Filed:

Jan. 12, 1993
Applicant:
Inventors:

Theodore C White, Tustin, CA (US);

Jayesh V Sheth, Mission Viejo, CA (US);

Dan T Tran, Laguna Niguel, CA (US);

Paul B Ricci, Laguna Niguel, CA (US);

Assignee:

Unisys Corporation, Blue Bell, PA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395325 ; 364D / ; 36424292 ; 3642281 ; 3642317 ; 36424341 ;
Abstract

A User bus lockout prevention mechanism for use in a time-shared busy multiple bus User, computer architecture where bus Users include private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetative cache cycles and periodicity of the Retry mechanism of the User. Bus lockout is prevented by the User with the cache issuing an INHIBIT WRITE to the bus when a cache cycle is being performed. Other Users inhibit issuing WRITE TO MEMORY requests to the bus until the INHIBIT WRITE signal terminates. Bus requests other than a write request may be issued to the bus during INHIBIT WRITE.


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