Data compression with pipeline processor having separate memories

Abstract

The compression system includes a series of pipelined data processors. Each processor has an associated memory. The body of digital data is applied serially to the first processor in the chain. The first processor analyzes pairs of data elements in its incoming signal to detect the occurrence of previously non-occurring sequences and stores those sequences in its associated memory. The output signal from the processor identifies the storage position in its associated memory of each pair of data elements in its input, whether or not those sequences have previously occurred in the data stream. Subsequent processors work with storage location signals only. Each processor provides a single output location signal for each pair of signals in its input. Each processor also determines the number of times that each incoming sequences has occurred and stores that number in association with each stored pair. A hashing table created by each processor and stored in its associated memory is used to segregate the stored pairs into groups having common lower significant figures to simplify the task of determining whether a pair of elements in the input has previously been stored. Pointers stored with each unique pair link the pairs in each hashed sequence in the order of their frequency of occurrence in the incoming data stream so that the incoming elements may be compared with the previously stored elements in the order of probability of occurrence of each pair in the data stream.