The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 08, 1994
Filed:
May. 28, 1992
Takahiko Hara, Kawasaki, JP;
Syuso Fujii, Kawasaki, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
In a CMOS-DRAM, an n-type silicon substrate has a p-type well formed therein, and a DRAM cell array is formed in the p-type well. In a period immediately after an external power supply is turned on, the p-type well is in a substantially floated condition. A predetermined time after the external power supply is turned on, the p-type well is applied with a predetermined DC voltage generated by a well voltage generating circuit. The CMOS-DRAM has a selective grounding circuit. When the external power supply is turned on, the selective grounding circuit forcibly grounds the plate electrode of the DRAM cell array for a predetermined period of time. Therefore, an increase in the well voltage at the cell array region, which increase may occur due to the capacitive coupling, is prevented when the power supply is turned on. Accordingly, adverse effects arising from the increase in the well voltage are prevented.