Circuit for glitch-free switching of asynchronous clock sources

Abstract

A circuit, including a state machine, e. g. a logic array and a set of controlled storage devices, receives conditioning signals, such as reset, power failure signals and signals fed back from the storage devices, and uses the signals to determine which of a number of clock sources is to be used in a system. The state machine provides output signals which are processed by a delay circuit to ensure that switches between clock sources only occur during an inactive period of the clock signals to prevent signal glitches. The circuit's output signal controls a number of AND gates, each of which gates a particular clock signal to an output line. When a power fail condition occurs, a switch between a first clock signal and a substantially lower frequency clock signal is required to conserve power. This is achieved by first switching to a synchronized lower frequency clock signal, and then to a non-synchronized lower frequency clock signal when the first clock signal is switched off since the synchronized low frequency clock signal is lost at this time when the clock source from which the first signal is generated is switched off to conserve power. A reverse process switches back to the high frequency clock without glitches when power returns.