Digital signal reproducing apparatus for reducing influence by jitter

Abstract

A fundamental period calculation circuit calculates a fundamental period in accordance with a plurality of pulses including reproduction target pulses included in binary reproduced output signal pulses sequentially input as digital signal pulses to be reproduced. A clock generator generates a demodulation clock having the fundamental period calculated by the fundamental period calculation circuit. A phase error amount detecting circuit detects a phase error amount in accordance with a phase difference between the demodulation clock generated by the clock generator and a plurality of pulses including the reproduction target pulses. A synchronizing circuit controls the phase error amount of a generation timing of the demodulation clock by the clock generator to a predetermined value in accordance with the phase error amount detected by the phase error amount detecting circuit so that the demodulation clock generated by the clock generator is synchronized with each of the reproduction target pulses. A demodulator sequentially demodulates the binary reproduced output signal pulses in accordance with the demodulation clock from the clock generator, the demodulation clock being synchronized with each of the reproduction target pulses with the predetermined phase error amount by the synchronizing circuit.