The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 1994

Filed:

Jun. 24, 1992
Applicant:
Inventor:

Yutaka Osada, Fujisawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11B / ; G11B / ; G11B / ;
U.S. Cl.
CPC ...
369 32 ; 369 4425 ; 369 4428 ; 369 54 ; 369 4434 ; 360 7804 ; 360 7805 ; 360 7807 ; 360 7811 ;
Abstract

A speed and position control apparatus comprising: an encoder generating two-phase signals having a 90-degree phase difference to correspond to a movement of a carrier; and adder obtaining a sum of phase signals; a subtracter obtaining a subtraction of phase signals; a circuit making bi-leveled signals from the sum and subtraction signals; a circuit obtaining an exclusive OR signal based on the bi-leveled signals; a circuit generating differential signals of respective phase signals; a first selector selecting either of the differential signals by the exclusive OR signal; a first switch selectively outputting an output of the first selector or its opposite-polarity output signal based on the bi-leveled subtraction signal; a second selector selecting either of the respective phase signals by the exclusive OR signal; a second switch selectively outputting an output of the second selector or its opposite-polarity output signal based on the bi-leveled subtraction signal; a device inputting an AC component of the second switch output signal to a sample and hold circuit; and a device returning an output of the sample and hold circuit, which holds a sample value inputted during a predetermined period of time in response to a building-up of the exclusive OR output signal, to its input terminal so as to realize a DC restoration.


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