The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 1994

Filed:

May. 08, 1992
Applicant:
Inventors:

Taisheng Feng, Austin, TX (US);

John D Porter, Austin, TX (US);

Jennifer Y Chiao, Austin, TX (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365226 ; 365 63 ;
Abstract

A memory (20) has N.sub.BIAS generators (63 and 73) coupled to the positive and negative power supply lines (61 and 62) at a point close to amplifiers (84 and 85) and address buffers (76) to insure that they all receive the same power supply voltage to prevent an impact on the access times of memory (20). A V.sub.CS generator (65) is located close to power supply bonding pads (23 and 25) and to output buffers (77 and 78) to reduce the effects of power supply line noise on the noise margins. A V.sub.AREF generator provides a reference voltage to the differential amplifiers of address buffers (75 and 76). Locating V.sub.AREF generator (67) close to power supply bonding pads (23 and 25) insures that the reference voltage is always at the midpoint of the input logic swing.


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