Serial memory apparatus having units for presetting reading bit lines to

Abstract

A memory apparatus includes a memory cell array in which a plurality of memory cells are arranged in a matrix formation and divided into blocks, a writing part for serially writing data to the memory cell array through a set of writing bit lines, each of the writing bit lines connected to one of the blocks, a reading part for serially reading the data from the memory cells of the memory cell array through a set of reading bit lines, each of the reading bit lines connected to one of the blocks, and a set of precharging units each for presetting one of the reading bit lines to a prescribed voltage when data is read from one of the blocks of the memory cell array. In this apparatus, when a first reading cycle is carried out to read data from one memory cell of a first block and a second reading cycle is consecutively carried out to read data from one memory cell of a second block lying consecutively to the first block, one of the precharging units presets the reading bit line connected to the second block to the prescribed voltage during the first reading cycle before the data is read from the memory cell of the second block.